Direct memory access controller: circuit, logic, states and operating mode. USB flash disk design

The embedded flash controller (EFC) is part of the memory controller (MC) and provides an interface for accessing flash memory blocks over an internal 32-bit bus. This allows you to significantly increase the speed of fetching instructions from flash memory when the processor core is running in Thumb mode (16-bit instruction system) due to the operation of a 32-bit buffer. Moreover, the embedded flash memory controller supports a full set of commands for reading, writing, erasing flash memory, setting and clearing security bits.

20.2 Functional description

20.2.1 Organization of built-in flash memory

The on-chip flash memory interfaces are directly connected to the internal 32-bit bus, which is built around several of the following interfaces.

• Simple memory organization: several pages of the same size.
• Two 32-bit read buffers designed to increase flash memory read speed (see "Read Commands" on page 101).
• One write buffer to store data when programming one page of flash memory. This buffer is the size of one page and is write-only. In addition, the write buffer addresses the entire 1 MB area of ​​flash memory (see "Write Commands" on page 101).
• Multiple protection bits (lock bits) to prevent flash memory from being erased or written to. Each protected area of ​​flash memory (all areas are of equal size) consists of a fixed number of pages arranged sequentially. Each such area is directly associated with only one protection bit.
• Several bits of non-volatile memory - NVM bits (Non Volatile Memory) for general purpose. Each of these bits is responsible for controlling certain nodes of the microcontroller. For more detailed information about each NVM bit, see the corresponding chapters of this document.

The size of the onboard flash memory, its page size, and the organization of security bits are described in Chapter 9, Memory.

Table 20-1. Number of security bits and general purpose NVM bits for AT91SAM7S family members

Figure 20-1. Built-in flash memory distribution map

20.2.2 Read commands

To speed up the flash memory reading process, the EFC controller has a dedicated 32-bit buffer built into it. Thanks to the presence of this buffer, when the processor operates in Thumb mode (16-bit instruction system), access to flash memory occurs half as often, thereby increasing the speed of fetching commands and, consequently, increasing the speed of the processor (Fig. 20-2, Fig. 20-3 and Fig. 20-4).

This optimization occurs only when fetching instructions, and does not occur when reading data from flash memory.

Read commands can be executed either without or with additional wait cycles. You can only set up to three wait cycles in the FWS (Flash Wait State) field of the MC_FMR Flash Mode Register (see "Flash Wait State Register", page 110). When FWS = 0, the on-chip flash memory is accessed in one cycle.

Flash memory can be accessed in 32-bit (dictionary), 16-bit (half-word), and 8-bit.

Since the size of the built-in flash memory is smaller than the microcontroller than the size of the address space of the internal memory allocated for it (1 MB), the memory controller implements the so-called. duplication of this block of flash memory throughout the entire address space allocated for it. For example, for the AT91SAM7S64, a 64 KB flash memory is mapped into this address space exactly 1024/64 = 16 times (translator's note).

Figure 20-2. Optimization when reading command code in Thumb mode for FWS = 0

Figure 20-3. Optimization when reading command code in Thumb mode for FWS = 1

Figure 20-4. Optimization when reading command code in Thumb mode for FWS = 3

20.2.3 Write commands

The area of ​​internal memory reserved for the built-in flash memory can also only be written through a special buffer. When executing write commands to flash memory, only the lower 8 bits of the address are taken into account (since we are talking about 32-bit data, the 10 least significant bits of the address are actually taken into account). In turn, the upper 10 bits of the address of the internal area (1 MB) reserved for flash memory address this so-called. a window whose size is 256 words (1024 bytes). Thus, this entire internal memory consists of 1024 such windows.

Any write command to the built-in flash memory can be prohibited by the MPU (Memory Protection Unit).

Flash memory can only be written to in a dictionary format (32 bits), so any attempt to write halfwords (16 bits) or bytes (8 bits) will produce an unpredictable result.

Write commands are executed in the number of wait cycles (FWS field in the MC_FMR register) specified for read commands, plus one additional cycle, except when FWS = 3 (see "Flash Mode Register", page 110).

20.2.4 Flash memory controller command system

EFCS includes commands for programming flash memory, commands for installing protection (unprotecting) its areas, commands for sequential programming and installing protection for flash memory, and a command for completely erasing all flash memory.

Table 20-2. Flash memory controller command system

Before executing any of the specified commands, the FCMD field of the MC_FCR register must contain the command code. Since the MC_FCR register is read-only, the FRDY flag is automatically cleared. When the instruction completes, the FRDY flag is automatically set, which can cause an appropriate interrupt if enabled through the memory controller (MC).

All flash memory commands are protected from accidental execution using one common keyword (keyword), which must be specified in the highest 8 bits of the MC_FCR register each time the next command is executed.

A command with an incorrectly specified keyword and/or an incorrectly specified command code will not be executed, even if the PROGE flag in the MC_FSR register is set. This flag will be automatically cleared the next time the MC_FSR register is read.

An attempt to execute a write or erase command on a page located in a protected area will have no effect on the contents of the flash memory (in fact, the command will be ignored), even if the PROGE flag in the MC_FSR register is set. This flag will be automatically cleared the next time the MC_FSR register is read.

Figure 20-5. Flowchart of the command execution process

For flash commands to execute correctly, the microsecond cycle time (FMCN) field in the Flash Controller Mode Register (MC_FMR) must be set to the correct value (see Flash Controller Mode Register, page 110).

20.2.4.1 Flash programming

Just a few commands can be used to program flash memory.

According to the technology of flash memory, it is mandatory to erase it immediately before programming it. Either erasing an entire flash memory area or a single page can be accomplished by clearing the NEBP flag in the MC_FMR register by directly writing the command code to the MC_FCR register.

By setting the NEBP flag in the MC_FMR register, a page can be programmed in a certain number of steps if it has already been cleared (see Figure 20-6).

Figure 20-6. Example of programming a section of a flash memory page

After the programming process is completed, the page can be protected from accidental or intentional erasure or writing (the entire area that the page is included in is protected). Using the WPL command, protection can be set automatically immediately after the end of the page write cycle.

The written data is stored in an internal buffer, the size of which is equal to the size of one page of flash memory. This internal buffer covers the entire address space of the internal flash memory, i.e. in fact, can be displayed in its entirety on any of its pages.

Note: writing in bytes (8 bits) or half words (16 bits) is prohibited, because how it causes distortion of the recorded data.

The process of writing data to flash memory, previously located in the internal buffer, is controlled using the flash memory command register (MC_FCR). Below is the sequence of working with this register.

• Writing an entire page, which can be located at any address within the entire flash memory address space, is only possible as a dictionary (32-bit data).
• The page write cycle begins immediately after the page number and the write command code itself are indicated in the MC_FCR register. This automatically resets the FRDY flag in the Flash Programming Status Register (MC_FSR).
• Immediately after the completion of the programming cycle, the FRDY flag in the Flash Programming Status Register (MC_FSR) is set. If interrupts from the FRDY flag are enabled, a corresponding interrupt signal will appear in the memory controller (MC).
• Programming Error: An invalid keyword and/or an invalid command was specified in the MC_FSR register.

20.2.4.2 Complete Erase Flash Command

All flash memory implemented on the chip can be cleared if the EA (Erase All) command is written to the MC_FCR register.

Erasing the entire flash memory is possible only when none of its areas are erasure-write-protected (not one of the flash memory protection flags is set). Otherwise (at least one of the protection flags is set), this command will be ignored. If the LOCKE flag in the MC_FMR register is set, the corresponding interrupt signal will occur.

After the last programming command or flash erase is executed, the MC_FSR register will automatically set the FRDY flag. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled.

During the programming cycle, errors may occur and are recorded in the MC_FSR register. Below are these errors.

• Programming Error: An invalid keyword and/or an invalid command was specified in the MC_FSR register.
• Lock Error: An attempt was made to program a locked area. To program this area correctly, it must first be unprotected using the unprotect command.

20.2.4.3 Flash protection bits

Each of the security bits is assigned to a specific area of ​​flash memory, consisting of a specific number of pages. The purpose of these bits is to protect flash memory from accidental or intentional erasure/programming.

During the manufacturing process of the microcontroller, some of the security bits may be set. Their purpose is to protect a certain area of ​​flash memory, which by default contains the program written to the microcontroller during its manufacture. Before programming/erasing a protected area, it must be unprotected.

The following is the sequence for installing protection for one area:

The following value should be written to the flash memory command register: (0x5A after the completion of the protection command, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled. ul>

After installing protection, it can be removed; below is the sequence for removing protection for one area:

• The following value should be written to the flash memory command register: (0x5A) After the completion of the protection command, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if enabled.

If an error occurs during the execution of a command (an incorrect keyword and/or incorrect command code is specified in the MC_FCR register), then this fact will be recorded in the MC_FSR register.

Executing a lock bit command physically writes a "1" to the corresponding bit, although when reading the MC_FSR register the corresponding LOCKx bit is read as a "0". Conversely, executing a set security bit instruction physically writes a "0" to the corresponding bit, and when reading the MC_FSR register, the corresponding LOCKx bit is read as a "1".

Note: Regardless of whether the flash memory is protected, it is still readable.

20.2.4.4 General purpose NVM bits

General purpose bits - NVM bits - are not associated with the built-in flash memory, but are intended to protect other components of the microcontroller. Each of these bits can be set (cleared) independently of the others. For details about NVM bits, see the relevant chapters in this document.

The following is the activation sequence for general purpose NVM bits.

• Execute the Set General Purpose NVM Bit (SGPB) command by writing the command code and the number of these bits in the PAGEN field of the same register to the Flash Command Register (MC_FCR).
• After the SGPB command completes execution, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled.

During the programming cycle, errors may occur and are recorded in the MC_FSR register. Below are these errors.

• The PAGEN field of the MC_FCR register indicates the number of general-purpose bits that is greater than the maximum allowable number of NVM bits implemented on the chip. Below is the sequence for clearing general purpose NVM bits.
• Execute the Clear General Purpose NVM Bit (CGPB) command by writing the command code and the number of these bits in the PAGEN field of the same register to the Flash Command Register (MC_FCR).
• After the CGPB instruction completes execution, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled.

During the programming cycle, errors may occur and are recorded in the MC_FSR register. Below are these errors.

• Programming error: An invalid keyword and/or an invalid command was specified in the MC_FSR register.
• The PAGEN field of the MC_FCR register indicates the number of general-purpose bits that is greater than the maximum allowable number of NVM bits implemented on the chip.

Executing the "clear general purpose NVM bits" command physically writes a "1" to the corresponding bit, although when reading the MC_FSR register the corresponding GPNVMx bit is read as a "0". Conversely, executing the "set general purpose NVM bits" command physically writes a "0" to the corresponding bit, and when reading the MC_FSR register, the corresponding GPNVMx bit is read as a "1".

Note: Regardless of the state of the general-purpose NVM bits, flash memory is always read-accessible.

20.2.4.5 Privacy bit

The security bit is intended to prevent external attempts to access the internal system bus. Once the security bit is set, the JTAG interface, the Flash Quick Programming Interface, and access to the Flash memory via the serial interface are disabled. Access to flash memory through the above interfaces is again allowed only when the crystal is completely cleared via the external ERASE pin - see Chapter 4. “Pin Assignments”. When a high logical level is applied to the ERASE pin (see section 7.4. “Erase control pin”), all flash memory implemented on the chip, all flash memory protection bits, and all general-purpose NVM bits are cleared, and only after all this is done clearing the privacy bit.

The following is the sequence for setting the privacy bit.

• Execute the Set Security Bit (SSB) command by writing the command code to the Flash Command Register (MC_FCR).
• After the SSB instruction completes, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if it is enabled.

Immediately after the security bit is set, the SECURITY flag in the MC_FSR register will be set.

Processor core of microcontrollers:
– arithmetic-logical device
– memory organization

Good afternoon, dear radio amateurs!
Welcome to the website ““

Today (more precisely, over the course of several articles) we will take a closer look at basis any microcontroller – processor core.

Essential elements:

1. Arithmetic-logical unit

ALU– the heart (and maybe the mind, with honor and conscience) of the microcontroller.
Here we will not play the role of a “dismemberment maniac” and tinker with the insides of this device. Let us only understand that thanks to the ALU, all the work of the microcontroller occurs. If you ever have a desire to learn more deeply how the “heart” of a microcontroller works (and it will be nice if it appears), then in the books of wonderful authors Belov, Ryumik, Evstifeev, Revich, Baranov and many others, you will always find a detailed answer .

2. Microcontroller memory (memory organization)

Before looking at microcontroller memory, let's talk a little about memory in general.
Human memory - everything is clear with it - it can be “solid” (when you are in solid memory, and sometimes also in your right mind) and, sadly, “holey”. And all information is stored in so-called “neurons” - small memory cells.
Almost everything is the same for microcontrollers. Only if a person has the smallest cell for storing information is called a “neuron”, then The smallest memory cell for a microcontroller for storing information is called “ bit“.
One bit can store either one logical one or one logical zero.
Bit – the minimum unit of measurement for memory capacity in microprocessor technology.
The next basic, or most common, unit of measurement for memory is byte.
Byte – that's eight bits of information. One byte can only store eight zeros and ones.
The maximum number that can be written to a byte is 255. If you operate with large numbers in the program, you should know (to know how many bytes are needed to store the number) that the maximum number that can be written to:
– one byte = 255
– two bytes = 65,535
– three bytes = 16,777,215
– four bytes – a number greater than 4 billion (if you are not in at least one hundred of Forbes magazine, then you will not need four bytes of memory to store numbers).
Writing to and reading from memory occurs in bytes (one bit of information cannot be written or read).
The next unit of measurement is kilobyte.
A kilobyte contains 1024 bytes of information. (exactly 1024, not 1000 bytes).
There are also large values ​​for measuring memory capacity (megabytes, gigabytes), but they are not yet used in microcontrollers.
I hope that everything is clear with the units of measurement of electronic memory:

Memory organization in a microcontroller

AVR chips have three types of memory:
– program memory, also known as FLASH memory
– data memory, also known as RAM (random access memory), aka SRAM
– non-volatile memory, also known as EEPROM, also known as EEPROM
In the microcontroller it is allocated three address spaces in which the above types of memory are located. In this case, the data memory (in the sense of an allocated address space) turned out to be a little deprived - it has to share its address space with memory cells in which general-purpose registers and I/O registers are stored (you will learn about them in detail in the next article). These registers do not physically belong to data memory, but are located in the same address space. If the starting addresses of program memory and non-volatile memory begin at address zero, then the starting address of data memory does not start at address zero - the general purpose registers and I/O registers take up space at address zero, and only the addresses of program memory cells follow them.
Some types of ATiny MKs do not have data memory.

Program memory (FLASH memory)

Program memory is designed to store our programs in it, as well as any data we need that does not change during program execution (constants). When the microcontroller is turned off, all data in the program memory is saved.
Program memory, of course, all microcontrollers have. The size of program memory, depending on the type of MK, varies from 1 kilobyte to 256 kilobytes.
Program memory access Only the programmer has access to the program memory when programming the MK; the MK itself also has access to program memory, but only to read data from memory; it cannot write anything there (you never know, it might suddenly want to ruin our program). True, the Mega family of microcontrollers has the ability (with the programmer’s permission) to make changes in program memory, but that’s a different story.
For program memory, there are two more types of memory size measurement - “ word" And " page“.
The fact is that program memory consists of cells consisting of two bytes. Such a cell is called a “word”. And this was done this way because almost all MK commands consist of two bytes, and, accordingly, to write them you need two bytes in program memory. Each MK command is one “word”. There are several commands that require 4 bytes in memory to write - two words, but such commands are found in microcontrollers that have a program memory of more than 8 kilobytes.
Thus, programs can be written into one cell of memory:
– any command consisting of two bytes
– half of the command, consisting of 4 bytes
– two constants, each of which fits into one byte, or one sixteen-bit constant. However, if you write three one-byte constants into memory, they will still occupy four bytes (two words) in memory.
Besides, writing to program memory is carried out not only in “words”, but also in “pages” . Page size ranges from 64 to 256 bytes (the larger the program memory, the larger the “page” size). What does it mean. If you created a small program, the size of which is 11 words (22 bytes), it will still take up one page of space in the program memory, i.e. at least 64 bytes. The “extra” 42 bytes will be filled with either zeros or ones. These are the pies.
But that's not all.
Program memory can have three states(if I may say so):
1. All memory is at the disposal of the programmer
In this case, we can completely fill the entire memory with our program and data. And the program will start from memory address zero.
2. Part of the memory is taken by the MK
If MKs are used during operation (and I hope you remember what they are), part of the MK’s memory is taken for the needs of interrupt processing and stored in it “ interrupt vectors“.
What it is.
When we allow the MK to process interrupts, it, starting from the zero memory address, takes part of the cells to store in them the addresses to which the MK needs to go to execute the interrupt subroutine. For each interrupt, the MK allocates two bytes of memory (one word) in which the addresses of interrupt handling routines are stored. These addresses, which indicate where the subroutine for processing a particular interrupt is located in memory, are called “ interrupt vectors“. And the entire memory area in which “interrupt vectors” are stored is called interrupt vector table. The number of occupied memory cells for interrupts depends directly on the number of possible interrupts of a given microcontroller (from several to several dozen). All interrupts are located at the beginning of the program memory, from address zero, and have a clear sequence. The reset interrupt vector is always located at address zero. When we turn on the device, or reset it with a button, the reset interrupt is triggered. The MK reads from the zero address (from the cell) the address that indicates where the beginning of our program is located in memory, and by going to this address it begins to execute the program. The program itself in this case will be located in program memory immediately behind the interrupt table.
3. The MK takes another part of the program memory (more precisely, it does not take it, but allocates an area at the end of the memory in which the programmer places a special program - the “loader”).
This is possible in MKs of the “MEGA” family, which have the ability to allow the MK to make changes to program memory. What does it mean.
Some MKs have the ability self-program. In the practice of amateurs, this possibility of MK is used extremely rarely. The ability to reprogram (self-program) is needed mainly in cases of industrial production of a device on a microcontroller, for which a software update can then be released. We will not consider this possibility, at least for now. We just need to know that in microcontrollers that support self-programming, the program memory is divided into two parts :
- top – application section, where our program and interrupt vectors are located
- lower – bootloader section (Boot Loader Section- in English), where the programmer places his loader program. The size of the bootloader section depends on the total size of the MK program memory, and can range from 128 bytes to 4096 bytes. If we do not use the ability to self-program the MK, then this section is given to our program and data.
Well, program memory is called FLASH memory because it is made using the so-called Flash technology (like the familiar computer “flash drives” to all of us).
The program memory allows 10 thousand reprogramming cycles.

Data memory (Static RAM, SRAM)

Random Access Memory, it's the same data memory type SRAM, is designed to store various data obtained as a result of the program.
When the microcontroller is turned off, all data stored in it is lost.
Data memory found in almost all microcontrollers (absent in the simplest MKs of the Tiny family).
In all MKs of the Mega family (and part of the MKs of the Tiny family), the amount of built-in data memory ranges from 128 bytes to 8 kilobytes, and almost all of it is at our complete disposal. He only takes a little MK for himself to organize the stack (we’ll find out what this is later). Some MKs provide for the connection of external memory (it can be of any type - FLASH, SRAM, EEPROM) with a capacity of up to 64 kilobytes. If external memory is connected to such MKs, it becomes, as it were, a continuation of the data memory.
Writing to and reading from data memory occurs byte by byte, and unlike program memory, it is not divided into pages and words.

Non-volatile memory (EEPROM)

Non-volatile memory also refers to data memory, but unlike the latter it has several features. It is designed to store data and constants that must be preserved in the absence of power.
All microcontrollers have EEPROM.
When the microcontroller's power is turned off, all data stored in non-volatile memory is saved (that's why it is called non-volatile).
Non-volatile memory capacity, depending on the type of MK, ranges from 64 bytes to 4 kilobytes.
Writing and reading information into memory is done byte by byte. However, in older models of the MEGA family, non-volatile memory, like program memory, has a page record. The page size is small, only 4 bytes. In practice, this feature does not matter - both writing and reading are carried out byte-by-byte anyway.
Number of write and erase cycles memory reaches 100,000.
The main feature of EEPROM is that when writing data to it, it becomes very “slow” - writing one byte can last from 2 to 4 milliseconds (this is a very low speed), and it can happen, for example, that during writing some - interruption, in which case the data recording process will be ruined.
In addition, it is not recommended to write data to non-volatile memory from address zero (I don’t remember the source of this information, but I definitely remember that I read it somewhere) - data may be damaged during operation of the MK. Sometimes programmers step back a few bytes from the beginning of the memory, and only start writing data in the next cells.

The basis of any flash memory is a silicon crystal on which not quite ordinary field-effect transistors are formed. Such a transistor has two insulated gates: control and floating. The latter is capable of holding electrons, that is, a charge. The cell, like any field-effect transistor, has a drain and a source (Fig. 4.1). During the writing process, a positive voltage is applied to the control gate and some of the electrons moving from drain to source are deflected towards the floating gate. Some of the electrons overcome the insulator layer and penetrate (diffuse) into the floating gate. They can remain in it for many years.

The electron concentration in the floating gate region determines one of the two stable states of the transistor - the memory cell. In the first, initial state, the number of electrons on the floating gate is small, and the threshold voltage for opening the transistor is relatively low (logical one). When enough electrons are supplied to the floating gate, the transistor is in the second stable state. Its opening voltage increases sharply, which corresponds to logical zero. When reading it is measured

Rice. 4.1. Flash memory cell

threshold voltage that must be applied to the drain to open the transistor. To remove information, a negative voltage is briefly applied to the control gate, and electrons from the floating gate diffuse back to the source. The transistor again goes into the logical one state and remains in it until the next write is made. It is noteworthy that in flash memory one transistor stores one bit of information - it is a cell. The entire “memorization” process is based on the diffusion of electrons in the semiconductor. This leads to two not very optimistic conclusions.

The charge storage time is very long and can be measured in years, but is still limited. The laws of thermodynamics and diffusion state that the concentration of electrons in different areas will sooner or later level out.

For the same reason, the number of write-rewrite cycles is limited: from one hundred thousand to several million. Over time, degradation of the material itself and pn junctions inevitably occurs. For example, Kingston Compact Flash cards are designed for 300,000 rewrite cycles. Transcend Compact Flash - on

1,000,000, and the Transcend 32 Gb USB flash drive is only 100,000,000.

There are two flash memory architectures. They differ in the way they access the cells and, accordingly, in the organization of internal conductors.

NOR (NOR) memory allows you to access cells one at a time. Each cell has a separate conductor. The address space of NOR memory allows you to work with individual bytes or words (each word contains

2 bytes). This architecture imposes serious restrictions on the maximum amount of memory per unit area of ​​the chip. NOR memory today is used only in BIOS chips and other low-capacity ROMs, such as cell phones.

In NAND (NAND) architecture memory, each cell ends up at the intersection of a “bit line” and a “word line.” Cells are grouped into small blocks, similar to a hard disk cluster. Both reading and writing are carried out only in whole blocks or lines. All modern removable media are built on NAND memory.

The largest manufacturers of NAND chips are Intel, Micron Technology, Sony and Samsung. The range of manufactured chips is quite large, and it is updated several times a year.

Controllers

The memory controller is used to control reading and writing. Currently, the controller is always implemented as a separate element (it is either a microcircuit of one of the standard form factors, or a bare chip built into a memory card), although work is underway to integrate the controller directly into a flash memory chip.

Controllers are developed and manufactured for completely specific flash memory chips. The method of addressing cells is structurally incorporated into the controller. When written to a flash memory chip, data is arranged in a certain way, which varies from model to model. Manufacturers keep these subtleties secret and, apparently, do not plan to disclose them. Obviously, much more controller firmware is created than the controller models themselves. The controller firmware (firmware) and address translation table (translator) are written to the service area of ​​flash memory. It is this area that the controller begins to read immediately after power is applied to it. In addition to the actual addressing of cells, the controller performs a number of other functions: functions of monitoring bad sectors, error correction (ECC - error check and correct) and uniform wear of cells (wear leveling).

The technological norm in the manufacture of memory chips is considered to be the presence of an average of up to 2% of non-working cells. Over time, their number may increase, therefore, as in hard drives, flash memory has a reserve capacity. If a defective sector appears, the controller, during the formatting or writing process, replaces its address in the file allocation table with the address of the sector from the spare area. The correction is carried out by the controller, but is implemented at the level of the file system of a specific media.

Due to the limited resource of the cells (on the order of several million read/write cycles for each), the controller has a function for accounting for uniform wear. To ensure that information is recorded evenly, the free space is conditionally divided into sections, and for each of them the number of write operations is taken into account. Cycle statistics are recorded in a hidden service memory area, and the controller periodically accesses it for this information. This does not affect addressing.

USB flash disk design

Despite the variety of cases, all USB flash drives are designed the same. If the case halves are connected with latches, they usually come apart easily. Waterproof or trendy cases have to be opened using destructive methods, such as cutting.

On the board inside the USB flash drive (Fig. 4.2) there are always two microcircuits: a memory chip and a controller. Both have factory markings. Sometimes the board carries two flash memory chips that work in pairs. The circuitry of the microcircuits consists of several resistors and diodes, a power stabilizer and a quartz resonator. Recently, the stabilizer is increasingly being built directly into the controller and the number of attachments is being reduced to a minimum. In addition, the board may contain an LED indicator and a miniature switch for write protection.

Rice. 4.2. Flash drive device

The USB connector is soldered directly to the board. The soldering points of the contacts in many models are quite vulnerable, since they bear mechanical load when connecting and disconnecting the device.

Types and design of memory cards

Many companies have offered different memory card designs to users from time to time. With rare exceptions, they are all incompatible with each other in terms of the number and arrangement of contacts and electrical characteristics. Flash cards come in two types: with parallel and serial interfaces.

In table 4.1 lists the 12 main types of memory cards that are currently found. Within each type there are additional varieties, taking into account which we can talk about the existence of almost 40 types of cards.

Table 4.1. Types of memory cards

Memory card type	Overall dimensions, mm)	Maximum constructive	Interface
CompactFlash (CF)			Parallel 50 pins
			Serial 9 pins
MultiMedia Card (MMC)			Serial 7 pins
			Serial 7 pins
Highspeed MMS			Serial 13 pins
			Serial 10 pins
Memory Stick PRO			Serial 10 pins
Memory Stick Duo			Serial 10 pins
SmartMedia (SSFDC)			Parallel 22 pins
			Parallel 22 pins
			Serial 8 pins

MMC cards can operate in two modes: MMC (MultiMedia Card) and SPI (Serial Peripheral Interface). The SPI mode is part of the MMC protocol and is used for communication with the SPI channel in microcontrollers from Motorola and some other manufacturers.

You can insert an MMC card (MultiMedia Card) into the SD (Secure Digital) card slot, but not vice versa. The SD card controller contains hardware data encryption, and the memory itself is equipped with a special area in which the encryption key is stored. This was done in order to prevent illegal copying of music recordings, for the storage and sale of which such a medium was intended. The card has a write protection switch.

CompactFlash (CF) cards can be easily inserted into the PCMCIA Type II slot. Although PCMCIA has 68 pins and CF has only 50, CompactFlash cards are designed to provide full compatibility and all the functionality of the PCMCIA-AT A format.

All Memory Stick media (a Sony standard) are relatively compatible with each other. The standard theoretically provides for a memory card capacity of up to 2 TB, although in reality the capacity reaches several gigabytes.

SmartMedia cards are almost obsolete and can only be found in very old digital cameras. It is noteworthy that this was the only standard in which the controller was not located inside the card, but in the reader.

The design of memory cards is non-separable - this device is unsuitable for repair. The unpackaged microcircuits, together with the leads, are poured into a compound and all together pressed into a plastic shell. The only way to get to the crystal is by opening the device, but this will almost inevitably damage the conductors.

Reading devices

To read a USB flash drive, a regular USB port is enough: the computer sees such devices as a standard removable drive thanks to their controller. The controllers of all memory cards face the computer via serial or parallel interfaces - contacts on the card. For each of these interfaces, you need a corresponding adapter - an additional controller that matches this interface with a standard USB port.

A card reader is a device consisting of one or more similar controllers, a power converter and connectors for different memory cards (Fig. 4.3). Power is supplied from a +5 V source via a USB cable.

Rice. 4.3. Card reader

Most often, there are “combines” designed for several types of cards: from 6 to 40. There are much fewer slots in a card reader, since each slot is used for several types of cards, similar in size and location of contacts. In terms of their characteristics, different models are almost equivalent, but differ mainly in the number of supported card types and design.

Logical organization

Before moving on to flash drive file systems, we need to remember the NAND architecture. In this frequently used memory, reading, writing, and deleting information occur only in blocks.

On hard and floppy disks, the block size is 512 bytes, not counting 59 service bytes, which are visible only to the hard drive controller. All file systems were created with these values ​​in mind. The problem is that in flash memory, the size of the erase block, with rare exceptions, does not coincide with the size of a standard disk sector of 512 bytes and is usually 4.8 or even 64 KB. On the other hand, to ensure compatibility, the read/write block must match the size of the disk sector.

To do this, the erase block is divided into several read/write blocks with a size of 512 bytes. In practice, the block is slightly larger: in addition to 512 bytes for data, it also has a “tail” (Tail) 16 bytes long for service information about the block itself. Physically, the location and number of read/write blocks are not limited in any way. The only limitation is that a read/write block must not cross an erase block boundary, since it cannot belong to two different erase blocks.

Read/write blocks are divided into three types: valid, invalid and defective. Blocks that contain written data and belong to a file are valid. Used blocks with outdated information are considered invalid and must be cleared. The category of defective blocks consists of blocks that cannot be written or erased.

Another feature of flash memory is that information can only be written to space that has been previously cleared of previous information. When information needs to be written, the controller firmware must decide which invalid blocks need to be erased first. In most firmware, the issue of removing invalid blocks is solved in the simplest way: as soon as a certain part of the flash disk capacity is filled with information, a mechanism for clearing invalid blocks is automatically launched.

To increase the service life of the memory, wear-leveling control technology is used, which extends the life cycle of the memory crystal by evenly distributing write/erase cycles of memory blocks. A side effect - the failure of one memory block - does not affect the operation of other memory blocks of the same crystal. Fixed blocks belong to files that have not been modified or moved for a long time or at all. The presence of stationary data blocks leads to the fact that the remaining part of the cells is subject to increased wear and tear and uses up its resource faster. The firmware takes such blocks into account and moves their contents to other cells as necessary.

File systems of flash disks and memory cards, at first glance, are well known to users from hard and floppy disks. This is FAT16, less often FAT32: this is how the Windows operating system suggests formatting the disk. Using standard Windows XP and Windows 7 tools, the disk can be formatted to NTFS! To do this, you must first go to Device Manager and in the properties window of the connected flash drive, on the Policy tab, select Optimization for fast execution. Special programs from manufacturers, such as HP USB Disk Storage Format Tool, allow you to format flash drives to NTFS without such effort.

However, the external similarity between the file systems of solid-state drives and conventional hard drives is deceptive. The flash file system (Flash File System, FFS) only emulates a regular disk drive and consists of control units and an initialization unit. In fact, only the flash disk or memory card controller knows about the true location and addressing of memory blocks.

This is very important for different methods of restoring the contents of a flash memory chip. When reading a memory chip through its “native” controller, the image file contains a sequence of blocks in the order of their numbers or offsets. At the beginning are the file system header and table. If reading is done on the programmer, the initial blocks of the dump contain service information, and the blocks with data are mixed almost randomly. In this case, service information is unlikely to be useful, since it entirely depends on the controller model and its firmware - the correct sequence of blocks has to be compiled with great difficulty.

Some cameras only work with the RAW file system. The method of recording photographs on media with such a file system, as well as the formatting features of the card itself, depend on the model of the device and even the firmware of a particular model. This format is not standardized and has many variations. Typically, data from such cards can only be restored by service programs from the camera manufacturer, and it is advisable to use the camera itself as a card reader.

Rice. 4.4. Window for formatting a flash disk in Windows Vista SPl

An innovation is the exFAT (Extended FAT) file system. Support for this file system specially designed for flash drives first appeared in Windows Embedded CE 6.0. Windows Vista Service Pack 1 and Windows 7 work with exFAT (Fig. 4.4).

The purpose of the new file system is to gradually replace FAT and FAT32 on flash drives. It contains some features that were previously unique to the NTFS file system:

The 4 GB file size limit has been overcome: theoretically the limit is 2^ bytes (16 exabytes);

Improved free space distribution by introducing a free space bitmap, which reduces disk fragmentation;

The limit on the number of files in one directory has been removed;

Added support for list of access rights.

Time will tell how soon this file system will become the norm for flash drives. Apparently, this will not happen until the vast majority of users switch to the Windows 7 operating system.

Sometimes when developing a device there is a need to save some data into non-volatile memory. In such cases, the internal EEPROM of the microcontroller is usually used. If it is not enough, then, as a rule, external EEPROM chips from the 24lxx series are used. Microcircuits in this series are very popular. Most often they can be found in old mobile phones, some motherboards, printer cartridges and many other places. The price of these microcircuits is also very attractive. For example, 24LC16 costs 11 rubles.
This chip is available in various packages, the most popular of which are DIP and SOIC. The microcircuit has the following pinout:

As you can see, there are very few conclusions. So let's try to figure out what's what.
A0, A1, A2- are not used in this microcircuit. They can be connected to ground or to the power supply positive. In some other 24lxx series microcircuits, these pins can set the address of the microcircuit, so that you can connect as many as 8 memory microcircuits to one i2c bus at once.
Vss- Earth.
S.D.A.- data line
SCL— clock line
W.P.- Write protection. When this pin is logic 0, writing to memory is enabled. If you apply a logical one, then only reading from memory is possible.
Vcc- power supply for the microcircuit. According to the datasheet, it is powered by voltage from 2.5 volts to 5.5 volts.

Connection to the controller.
Connecting memory to the MK is very simple. From the wiring you only need a pair of resistors with a resistance of about 4.7 kOhm.

Software

To work with memory, a library was developed that implements the following functions:

i2c_init— adjusts the speed of clock pulses traveling along the line SCL.

The 24LC16 chip supports frequencies up to 400 kHz. You can calculate the frequency like this:

CPU Clock frequency— frequency at which the microcontroller operates

TWBR— a number written in the register of the same name.

TWPS- predivider. Prescaler values ​​are specified by bits TWPS1 and TWPS0 in the TWSR register

For the Atmega 32 controller, the following table is valid:

i2c_start— sends the starting package

i2c_stop— sends a stop message

i2c_send- sends a byte

i2c_receive— receives a byte

i2c_recive_last— accepts the last byte. The difference from the previous function is that when a byte is received, the microcontroller does not send an acknowledgment bit. If, when receiving the last byte, use i2c_receive then the SDA line will remain pressed to the ground.

Writing data to a memory chip

You can record data either in random order or page by page. Since there can be several devices on the i2c bus at once, in order to access any device you need to know its seven-bit address. The address of the 24LC16 chip in binary looks like this:

Bits A,B,C are used to select a memory block. There are 8 memory blocks in the chip, 256 bytes each. Accordingly, the ABC bits take values ​​from 000 to 111.

In order to write a byte to the chip, you need to perform the following sequence of actions:

1. Initialize i2c interface
2. Send the starting package
3. Send chip address + memory block address
4. Send the address of the memory cell to which the recording will be made
5. Send data byte
6. Send a stop package

Example: Need to write a byte 0xFA by the address 0x101.

rcall i2c_init
rcall i2c_start
ldi temp,0b 1010 001 0 //Chip address where:
// 1010 - chip address
// 001 - memory block address (Cell 0x101 belongs to block 1)
// 0
rcall i2c_send
ldi temp,1 //Address of the memory cell. (block 1, cell 1)
rcall i2c_send
ldi temp,0xFA //Load the byte that needs to be written into the register
rcall i2c_send //Write a byte
rcall i2c_stop

You can write data to memory not only byte by byte but also page by page. Page size is 16 bytes. The post-process recording implies the following: We send the address of the zero byte of the desired page and after that we send the necessary data 16 times. The address counter will increase by one automatically. If you send data for the 17th time, the zero byte will be overwritten, if you send the byte 18th time, it will overwrite byte number 1, etc.

Example: The first page of block 0 needs to be written.

rcall i2c_init //Initialize the i2c interface
rcall i2c_start // Send the starting package
ldi temp,0b 1010 000 0 //Chip address where:
// 1010 - chip address
// 000 - address of the memory block (we are interested in block zero)
// 0 - read/write bit. 0 - write, 1 - read
rcall i2c_send
ldi temp,16 //Address of the first page
rcall i2c_send
ldi temp,0x01 //Load byte number 0 into the register
rcall i2c_send //Write a byte
ldi temp,0x02 //Load byte number 1 into the register
rcall i2c_send //Write a byte
/// here we write the remaining bytes.....
ldi temp,0x0E //Load byte number 14 into the register
rcall i2c_send //Write a byte
ldi temp,0x0F //Load byte number 15 into the register
rcall i2c_send //Write a byte
rcall i2c_stop //Send a stop package

Reading data from the chip
We seem to have sorted out the recording, now let's start reading. To read a byte you need to do the following:

1. Initialize the i2c interface (if it has not been initialized previously)
2. Send starter package
3. Send the address of the microcircuit and the address of the memory block from where we will read
4. Send memory cell address
5. Resend the starting package
6. Send chip address and memory block address with “read” bit
7. Get byte
8. Send stop parcel

rcall i2c_init //Initialize the i2c interface
rcall i2c_start // Send the starting package
ldi temp 0b1010 011 0 //Chip address + address of the 3rd memory block.
//Read/write bit is still 0!
rcall i2c_send
ldi temp,0x41 //Memory cell address
rcall i2c_send
rcall i2c_start //Re-sending the starting package
ldi temp 0b1010 011 1 //Chip address+memory block address+read/write bit becomes 1
rcall i2c_send //now you can read the data
rcall i2c_recive_last //Read the byte. First and last.
rcall i2c_stop //Send a stop package

Reading can be done sequentially byte by byte, i.e. just calli2c_receive As much as needs. There is no need to send a command to increase the address by one. There is also no need to switch block addresses when reading sequentially. Those. you can take and read the entire microcircuit at once without any problems.

The library for working with i2c was developed and tested on the Atmega32 microcontroller. I think it will work on many other controllers without any modifications. Naturally, the controller must have hardware support for i2c or as it is also called TWI. Of course, i2c can be implemented in software, but I didn’t bother and there was no need. The demo example is a program that writes bytes from 0 to 15 to the first 16 addresses, and after writing, outputs them to port A. You can see how this works not only live, but also in Proteus.

And finally, I’m attaching an oscillogram:

This is what the i2c bus looks like through my eyes :-)
I welcome all questions and suggestions in the comments.

As an example of implementing the principles of direct memory access (DAM), let's consider the KR580VT57 microcircuit. The programmable DMA controller is designed for high-speed data exchange between the system memory and four external devices (ED).

The controller carries out bidirectional data exchange between the memory and the computer (at the request of the computer), while the parameters of a given array of addresses of memory cells (starting address and number of cycles) and control signals are formed in the address channel of the microprocessor system. Each of the four controller channels provides addressing (by incrementing the generated address) of external memory in arrays of up to 16K bytes with the ability to set any of the 64K starting addresses.

Composition of the DDP controller

The following blocks can be distinguished in the controller (Fig. 3.11.1): a request processing block, an address generator, a read-write logic block, a control block, a data buffer and two registers - the mode setting register and the channel status register. Let's consider their features.

The request processing block is designed to:

● for reception request signals ZPDP0–ZPDP3 for direct memory access from the host;

● for masking channel inputs K0–K3;

● for issuance request confirmation signals ¯PPDP0 – ¯PPDP3 direct memory access, informing the host that the controller is ready to exchange data via the DMA channel.

The address generator contains 16-bit registers of the starting address (РНА0...РНА3) and the number of cycles (РЧЦ0...РЧЦ3), an increment-decrement circuit, and a trigger. During the execution of the initial installation program, the starting address of the memory cell to which the computer will access via the DMA channel is written to the PHA. The number N – 1 is entered into the 14 low-order digits of the register for the number of RFC cycles, where N is the number of cycles. The two most significant bits of this register are used to control traffic over the DMA channel.

In each cycle, two address bytes are read from the PHA. The trigger ensures the reading order: the high byte is output through the data buffer to the SD, and the low byte of the address is output via buses A0...A3, A4...A7. At the end of the cycle, the increment-decrement scheme increases the contents of the PHA and decreases the contents of the RFC by one. It should be noted that the controller pins A4...A7 are always used as outputs for bits A4...A7 of the address code, and pins A0...A3 are used:

• How exits for transmitting low-order bits of the address code during operation of the DMA channel;
• How inputs to select the register with which information will be exchanged. This need arises when writing the initial installation program to the DMA controller, as well as when reading the contents of the address register, the number of cycles register or the status register.

Read-Write Logic Block

Receives, generates and issues signals that ensure the exchange of information between the processor and the DMA controller, memory and computer. The read-write logic block has the following pins:

● ¯Зп - bidirectional control three-stable input/output, used:

How entrance for receiving a signal from the processor to record data into the internal registers of the DMA controller during its initial installation;

How exit, on which a signal is generated that allows an external device record data from memory;

● ¯Tch - bidirectional three-stable control input/output used:

How entrance to receive a signal from the processor allowing reading(output) the contents of the internal registers of the controller;

How exit for issuing a signal for permission reading data from the computer to memory;

● ¯ChtP, ¯ZpP - outputs for controlling reading from memory and writing to memory;

● ¯ВК - input (chip selection), to which the zero chip selection signal is supplied after the write or read signals are set. The ¯ВК signal initiates data exchange between the processor and the internal registers of the DMA controller during programming; automatically locked in direct access mode. The ¯ВК input is connected to the microprocessor system ША directly or through a decoder.

The pins ¯Зп, ¯Чт are connected to the processor as inputs and to the computer as outputs, and the outputs ¯ЗпП, ¯ЧтП - to the memory of the microprocessor system.

At the stage initial installation in the address generator, the low-order bits A3...A0 of the address code are deciphered and after receiving the signals ¯Зп, ¯Чт from the processor, writing or reading of programmatically accessible registers of the DMA device is organized. At work in a cycle The DDP logical circuits of the read-write block form pairs of signals ¯Cht, ¯ZpP and ¯Zp, ¯ChtP at the outputs of the device, which provide clocking of the data exchange process between the computer and memory.

Control block

regulates the sequence of operations during all DMA cycles using control signals, and also transitions the controller from the standby state to the service state using the capture confirmation signal (PZx). The control unit has the following outputs:

• ЗЗх (Н RQ) - output from which the signal is taken capture request for microprocessor;
• ПЗх (HLDA) - input to which the signal is received capture confirmation from microprocessor;
• GT (RDY) - control input readiness. The signal Гт = 1 from the control unit activates the operation of the PDP controller; signal Гт = 0 puts the controller into the standby state;
• M128 - exit 128th cycle marker: M128 = 1 indicates that the current DAP cycle is the 128th cycle from the end of the data array;
• KS (TS) - exit end of count: KS = 1 indicates to the host that the current exchange cycle on the DMA channel is the last one when transmitting a data array. If the “KS-stop” bit in the mode setting register is set to 1, the channel will be disabled. The KS output is activated (KS = 1) when the contents of the 14-bit register of the number of cycles in a given channel are set to 0;
• RA (AE) - exit address permissions: PA = 1 indicates to the system that forward access cycles are occurring. In this case, all buses are disconnected from the microprocessor. The signal can be used to block the address bus in devices not participating in direct access, as well as to write the upper eight bits of the address code to the address buffer register and disable the device's sampling circuit. In the DMA mode, the device is sampled using the signals ¯PPDP0 – ¯PPDP3;
• STBA - exit address strobe, the signal of which is strobed by the high byte of the memory address, transmitted through the SD to the additional data buffer. Through this buffer, the high byte of the address is supplied to the address bus of the microprocessor system;
• TI - input for clock pulses;
• Reset is the initial device setup input. Applying a single signal to this input resets the contents of all software-accessible registers, which leads to the disabling of channels K0 - K3.

The data buffer is an 8-bit bidirectional bus with three states connecting the DMA controller to the SD system data bus.

Via data buffer:

• at programming in write mode, eight data bits D 7 ... D 0 from the microprocessor are transferred to the DMA controller for writing to the start address register, the number of cycles register or the mode setting register; when the processor reads from the DMA device, the contents of the starting address register, the number of cycles register and the channel status register are output;
• at channel work At the beginning of each DMA cycle, the upper eight bits of the address are transferred from the address register of the corresponding channel to memory. Then the SD is freed for direct data exchange between memory and host device during the remainder of the cycle. This data does not pass through the DDP device.

Installation register

modes stores information about the programmed modes of autoloading, extended and normal recording, fixed priority and cyclic shift of priorities, KS-stop, etc. When programming the DMA controller, an 8-bit control word is written to it. The mode setting register is usually loaded after the address register(RgA) and loop register(RgC). The purpose of the mode setting register bits is given in table. 3.11.1.

Channel Status Register

indicates in which of the four channels the array transmission process has ended. To do this, the value of the signal KS = 1 of the end of the count, which appears at the output of KS and indicates the end of the array via the corresponding channel, is written to the low-order bits PC0–PC3 (service completion flags). Purpose of categories mode setting register given in table. 3.11.2.

Basic states and operating modes of the device.

The main conditions are initial state, programming, waiting and maintenance.

The initial state.

Upon arrival at the entrance Reset single signal the device goes into original state. In this state, requests from all DMA channels are masked (P0 = P1 = P2 = P3 = 0), and the buffer circuits of the bus A0...A3 are transferred to the state of receiving information.

Programming.

Able programming device, the microprocessor via the data bus (SD - D 0... D 7) writes the starting address, number of cycles and other data into the corresponding registers, the address of which is specified by code A 3 A 2 A 1 A 0 on buses A0–A3 (Table 3.11. 3). The most significant bit of the A3 code allows you to distinguish when A3 = 0 - channel registers K0...K3; at A3 = 1 - mode setting register(works only for recording) and channel status register(read only). The least significant bit A0 selects the starting address (A0 = 0) and number of cycles (A0 = 1) registers. The two middle digits A 2 A 1 indicate the numbers of registers (or channels) in binary code. For example, code 0101 corresponds to RFC2 - the register for the number of cycles of channel 2. The registers of the DMA controller are loaded or information is read from them if the microprocessor executes a write or read command by accessing the device and its registers. To do this, the microprocessor needs to issue the corresponding write signals ¯Зп or read ¯Пт and set the register address in the form of code A 3 A 2 A 1 A 0 to the system address buses ША. At this time, the necessary information D 7 ... D 0 is supplied to the SD data bus for writing to registers, or information from the DMA controller is read through the SD data bus. To set the programming state, it is also necessary to apply the device sampling signal ¯ВК = 0. Due to the fact that the channel registers are 16-bit, two program instruction cycles are required to load or read them. IN address generator The controller has a trigger that automatically switches circuits during a read or write operation. This trigger determines access to the high or low bytes of the register. The trigger is reset by applying a single signal to the input Reset and also whenever the mode setting register is loaded.

To ensure appropriate synchronization when accessing channel registers, all commands must come from the microprocessor in pairs, and there should be no gaps between them.

Expectation.

Able expectations The controller receives a request signal from the computer to receive a DMA cycle (ZPDP0–ZPDP3) and generates a capture request signal (ZZx) for the microprocessor. In this state, the system buses are controlled by the microprocessor.

Service.

After receiving a capture confirmation signal (PZx) from the microprocessor, in the presence of a request signal (ZPDP0 - ZPDP3) from the CU, the controller generates a request confirmation signal (¯PPDP0 - ¯PPDP3) for one of the CUs and goes into service status. IN In this state, the system buses are under the control of the controller, and one of the programmed DMA modes is implemented:

• the lower 8 bits of the memory address go to buses A0–A3, A4–A7, the highest 8 bits go to the SD data bus;
• corresponding control signals ¯ChtP and ¯ZpP, ¯Zp and ¯Cht are generated, which allow the computer to receive a byte of data from a memory cell or transfer it to a memory cell in one cycle.

In the first cycle of operation, the DMA device transmits the starting address of the memory cell. In subsequent cycles, the address increases, and the number of cycles decreases by one, until the contents of the number of cycles register (or rather its 14 bits) becomes equal to zero. After this, a signal is generated end of account KS and the following operating modes are possible:

• further increase of the address by adding one after the next cycle;
• blocking the DMA channel ("KS-stop" mode);
• repeating a previously selected array of addresses (autoload mode).

During the execution of DMA cycles, three operating modes are possible:

• mode reading, providing data transfer from memory to the computer;
• mode records, providing data transfer from the computer to memory;
• mode checks. In this mode, the DMA controller does not generate the signals ¯ChtP, ¯ZpP, ¯Rh and ¯Zp, which prevents data exchange between the memory and the host. However, in each cycle the DMA controller controls the system bus and confirms the host requests. External devices can use acknowledgment signals to allow internal access to each byte in the data array in order to perform some verification operations. An array of check cycles may follow the array of read cycles to allow the host to check newly arrived data.